1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to the manufacture of N-channel field effect transistors having a strained channel region caused by a stressed dielectric material formed above the transistor.
2. Description of the Related Art
Integrated circuits typically comprise a large number of circuit elements on a given chip area according to a specified circuit layout, wherein, in complex circuits, the field effect transistor represents one important device component. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry based on field effect transistors, such as microprocessors, storage chips and the like, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using MOS technology, millions of transistors, in CMOS technology, complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, the conductivity of the channel region represents an important factor that substantially affects the performance of MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, may be dominant design criteria for accomplishing an increase in the operating speed of integrated circuits.
The shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One problem in this respect is the reduction of the thickness of the gate dielectric layer in order to maintain the desired channel controllability on the basis of increased capacitive coupling. With the thickness of oxide-based gate dielectrics approaching 1.5 nm and less, the further scaling of the channel length may be difficult due to an unacceptable increase of leakage currents through the gate dielectric. For this reason, it has been proposed to enhance device performance of the transistor elements not only by reducing the transistor dimensions but also by increasing the charge carrier mobility in the channel region for a given channel length. One efficient approach in this respect is the modification of the lattice structure in the channel region, for instance, by creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region of a silicon layer having a standard crystallographic configuration may increase the mobility of electrons, which in turn may directly translate into a corresponding increase in the conductivity for N-type transistors. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. Consequently, it has been proposed to introduce, for instance, a silicon/germanium layer or a silicon/carbon layer in or near the channel region to create tensile or compressive stress. Although the transistor performance may be considerably enhanced by the introduction of strain-creating layers in or below the channel region, significant efforts have to be made to implement the formation of corresponding strain-inducing layers into the conventional and well-approved CMOS technique. For instance, additional epitaxial growth techniques have to be developed and implemented into the process flow to form the germanium- or carbon-containing stress layers at appropriate locations in or below the channel region. Hence, process complexity is significantly increased, thereby also increasing production costs and the potential for a reduction in production yield.
Therefore, a technique is frequently used that enables the creation of desired stress conditions within the channel region of different transistor elements by modifying the stress characteristics of a material that is closely positioned to the transistor structure in order to allow an efficient stress transfer to the channel region. For example, the spacer typically provided at sidewalls of the gate electrodes and the contact etch stop layer that is formed above the basic transistor structure are promising candidates for creating external stress which may then be transferred into the transistor. The contact etch stop layer is, therefore, frequently used since it may be required anyway for controlling an etch process designed to form contact openings to the gate, drain and source terminals in an interlayer dielectric material. The effective control of mechanical stress in the channel region, i.e., an effective stress engineering, may be accomplished for different types of transistors by individually adjusting the internal stress in the contact etch stop layers located above the respective transistor elements to position a contact etch stop layer having an internal compressive stress above a P-channel transistor while positioning a contact etch stop layer having an internal tensile strain above an N-channel transistor, thereby creating compressive and tensile strain, respectively, in the respective channel regions.
Typically, the contact etch stop layer is formed by plasma enhanced chemical vapor deposition (PECVD) processes above the transistor, i.e., above the gate structure and the drain and source regions, wherein, for instance, silicon nitride may be used due to its high etch selectivity with respect to silicon dioxide, which is a well-established interlayer dielectric material. Furthermore, PECVD silicon nitride may be deposited with a high intrinsic stress, for example, up to 2 Giga Pascal (GPa) or significantly higher compressive stress, while stress levels of 1 GPa and higher may be obtained for tensile-stressed silicon nitride materials, wherein the type and the magnitude of the intrinsic stress may be efficiently adjusted by selecting appropriate deposition parameters. For example, ion bombardment, deposition pressure, substrate temperature, the type of gas components and the like represent suitable parameters that may be used for obtaining the desired intrinsic stress. As explained before, the contact etch stop layer is positioned close to the transistor so that the intrinsic stress may be efficiently transferred into the channel region, thereby significantly improving the performance thereof. Moreover, for advanced applications, the strain-inducing contact etch stop layer may be efficiently combined with other strain-inducing mechanisms, such as strained or relaxed semiconductor materials that are incorporated at appropriate transistor areas in order to also create a desired strain in the channel region. Consequently, the stressed contact etch stop layer is a well-established design feature for advanced semiconductor devices.
However, in actual integration schemes for selectively providing a tensile-stressed dielectric material and a compressively-stressed dielectric material above respective transistor elements, it may be observed that, in particular, the performance of N-channel transistors may not be enhanced as efficiently as expected. With reference to FIGS. 1a-1d, a corresponding integration scheme may be described in which a tensile-stressed dielectric material may be deposited first, thereby resulting in a less pronounced performance gain for N-channel transistors.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, such as a silicon substrate and the like, above which is formed a silicon semiconductor layer 102. In and above the semiconductor layer 102, an N-channel transistor 150A and a P-channel transistor 150B may be formed. The transistors 150A, 150B may differ in other aspects of their device configuration in addition to their conductivity type, depending on the overall device requirements. The transistors 150A, 150B may represent a complementary transistor pair or may represent transistor elements which may be located at specific device regions. Although the transistors 150A, 150B may differ in their configuration, for convenience, any such differences are not shown in FIG. 1a. Thus, the transistors 150A, 150B may comprise a gate electrode 151, which may be comprised of polysilicon and the like, depending on the device requirements. Furthermore, a gate insulation layer 152 separates the gate electrode 151 from a channel region 153 which in turn is laterally bordered by drain and source regions 154. Furthermore, metal silicide regions 155 may be provided in the drain and source regions 154 and in the gate electrode 151. As shown, the gate electrode structure may have formed on sidewalls thereof a spacer structure 156, which may be comprised of a plurality of individual spacer elements, possibly in combination with appropriate liner materials, according to well-established spacer concepts. In the manufacturing stage shown in FIG. 1a, the device 100 may further comprise an etch stop layer 103 comprised of, for instance, silicon dioxide, followed by a tensile-stressed contact etch stop layer 110, formed of the silicon nitride having a high intrinsic tensile stress. Moreover, an etch control layer 104, for instance, in the form of silicon dioxide, is formed on the stressed contact etch stop layer 110. Thus, the internal stress of the layer 110 is selected to enhance performance of the N-channel transistor 150A, as previously explained.
Typically, the device 100 as shown may be formed on the basis of the following processes. After patterning the gate electrode structure 151 and the gate insulation layer 152, the drain and source regions 154 may be defined, for instance, on the basis of the spacer structure 156, wherein respective individual spacer elements may be provided to act as an efficient implantation mask, depending on the desired lateral and vertical dopant profile for the drain and source regions 154. The dopant within the drain and source regions 154 and implantation-induced damage may be annealed, resulting in activated dopants and a re-crystallized lattice in the drain and source regions 154. Thereafter, the metal silicide regions 155 may be formed on the basis of well-established techniques, for instance, including the deposition of an appropriate refractory metal followed by a heat treatment for initiating a chemical reaction. After removal of any non-reactive metal material, the etch stop layer 103 may be deposited, for instance, by PECVD in the form of silicon dioxide having a desired density and thickness as may be desired for a subsequent usage as an etch stop layer, when patterning the contact etch stop layer 110. Next, the layer 110 may be deposited on the basis of appropriately selected deposition parameters, as previously explained, in order to deposit silicon nitride material with reduced density, and thus a high internal tensile stress, as may be desired for performance enhancement of the transistor 150A. For instance, during the deposition process, in particular, the degree of ion bombardment may be efficiently used for controlling the magnitude and type of internal stress. Thereafter, the etch control layer 104, for instance, in the form of a silicon dioxide material which may have a reduced density, depending on the deposition parameters, is formed, possibly in an in situ process with respect to the layer 110.
FIG. 1b schematically illustrates the semiconductor device 100 during an etch process 105 which is performed on the basis of a resist mask 106 that covers the N-channel transistor 150A. The resist mask 106 may be formed on the basis of well-established photolithography techniques, while, for the etch process 105, a plurality of appropriate etch recipes are available. For instance, the etch control layer 104 may be removed on the basis of any appropriate etch chemistry for etching silicon dioxide material, for instance, in the form of a dry or wet chemical etch step. Thereafter, well-established plasma-assisted etch recipes may be used for etching the exposed portion of the layer 110 selectively to the etch stop layer 103. For instance, respective etch techniques are well established from conventional spacer techniques and may also be used in this case. The etch stop layer 103 may thus reliably protect sensitive device areas, such as the metal silicide regions 155 in the transistor 150B. Depending on the overall process strategy, the layer 103 may be removed from above the transistor 150B, however, on the basis of a less aggressive etch recipe, thereby not unduly affecting the metal silicide regions 155.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage in which a compressively stressed contact etch stop layer 120 is formed above the transistors 150A, 150B. Additionally, a resist mask 107 protects the transistor 150B during an etch process 108 designed to remove the exposed portion of the compressively stressed layer 120 above the N-channel transistor 150A. The etch process 108 may be carried out on the basis of the etch control layer 104, which may create an appropriate endpoint detection signal, that is, an appropriate spectral intensity of radiation of the gaseous ambient created during the etch process 108, when the etch front encounters the etch control layer 104. After removing the exposed portion of the compressively-stressed layer 120 and any residues of the etch control layer 104, the further processing may be continued by depositing an interlayer dielectric material. For this purpose, well-established PECVD techniques on the basis of TEOS (tetra ethyl orthosilicate) are used to provide silicon dioxide material at a high deposition rate with desired chemical and mechanical characteristics. Thus, the transistors 150A, 150B may be enclosed by the silicon dioxide-based material, the surface topography of which may be planarized, for instance, by chemical mechanical polishing (CMP) in which the high-mechanical integrity of the silicon dioxide material may result in higher process robustness.
FIG. 1d schematically illustrates the semiconductor device 100 after finishing the above-described process sequence. Hence, the device 100 comprises a silicon dioxide material 109 acting as an interlayer dielectric material and having a substantially planar surface configuration. Thereafter, a respective photolithography process may be performed in order to create an etch mask for patterning the interlayer dielectric material 109 to thereby produce respective openings 109A, which are illustrated in dashed lines, and in which finally a metal material is to be deposited. During a corresponding patterning process, the contact etch stop layers 120, 110 may be used as etch stop materials, which may be opened in a separate etch step so as to finally connect to the drain and source regions 154 and to the gate electrodes 151.
During operation of the semiconductor device 100, performance of the transistor 150B may be significantly enhanced due to the high compressive stress which generates a respective compressive strain in the channel region of this transistor. Similarly, performance of the transistor 150A may be enhanced, however, at a significantly lower degree compared to what would be expected on the basis of the initially created tensile strain of the layer 110. Thus, although the dual stress liner approach described above is well established and provides various advantages compared to other strain-inducing mechanisms, performance enhancement, in particular for N-channel transistors, may not be fully exploited by the conventional strategies.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.